To ensure the operability of a memory cell, including storage devices such as registers or latches, each individual device is usually tested after fabrication. The devices are tested by storing a known pattern into the stored cells of the device and subsequently reading the contents of the device. If the data input to the device is not identical to the data output from the device, then the device is discarded as having one or more failed cells. To detect hard failures, where a memory cell is always one or always zero, the device is tested with different patterns, such that each cell is tested for its ability to successfully store both logic states.
Silicon-on-insulator (SOI) technology is becoming of increasing importance in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material which overlies an insulating layer. A common embodiment of SOI structures is a single crystal layer of silicon which overlies a layer of silicon dioxide.
The structure of an SOI transistor presents a parasitic "back channel" transistor, with the substrate serving as the gate and the insulator film underlying the transistor serving as the gate dielectric. This back channel may provide for a drain-source leakage path along the body node near the interface with the insulator film. A goal in the design of SOI transistor devices is to maximize the back gate threshold voltage so that the possibility of a back channel leakage path is eliminated.
Application of radiation to an SOI transistor device can detrimentally effect the back gate threshold voltage due to charge trapping in the insulator. In many military and space applications, the amount of radiation a circuit can withstand, or the radiation hardness, is specified. This specification must be reliably met for all devices to be utilized in these applications.